1. Field of the Invention
This invention relates to a semiconductor device. In particular, the invention relates to a semiconductor device suitable for surface packaging in a manner in which a number of semiconductor devices are mounted together on substrates and are encapsulated in moulding compound.
2. Description of the Related Art
In the prior art, it is the general practice, as shown in FIGS. 1 to 3, to compose a plastic-encapsulated semiconductor device for surface packaging by mounting a semiconductor element 3 on the surface of a plate-shaped die-pad 2 supported at the four corners by tie-bars 1. After bonding semiconductor element 3 and lead wires 4 by bonding wires 5, a semiconductor package P is constructed by sealing this in moulding compound 6.
At this time, the tie-bar lengths L between the corners of die-pad 2 and the ends of tie-bars 1 have values determined by the external measurements of semiconductor package P.
However, in line with recent high-density packaging, there are advances in the application of thin plastic-encapsulated packages for surface mounting such as FP (Flat Package), PLCC (Plastic Leaded Chip Carrier) and SOJ (Small Outline J-bend Package). When carrying out the surface mounting of such semiconductor packages on substrates, a method is used in which the whole of the semiconductor package is exposed to a high temperature of 200.degree. C. or more, which is quite different from heat-soldering only the individual leads.
Because of this, the water content absorbed inside moulding compound 6 tries to vaporise explosively at the interfaces between semiconductor element 3 and moulding compound 6, and between die-pad 2 and moulding compound 6. Thus, high pressure is applied to both interfaces, so that, as shown in FIG. 3, there are problems of cracks 7 occurring in the lower part of moulding compound 6 around die-pad 2 and in the upper surface of moulding compound 6 (not illustrated) around semiconductor element 3.
Not only do these cracks 7 spoil the external appearance, they also lead to a substantial degradation of the moisture resistance reliability of semiconductor element 3.
In order to prevent the occurrence of these cracks, Japanese Laid Open Patent (Showa) 60-208847, for example, proposes methods in which columnar or polygonal holes are punched in the moulding compound at the back of the semiconductor element, to form sections with an extremely thin flash or in which there is no moulding compound. Thus, when heating the semiconductor package as a whole the gas due to vaporisation of the internal water content is allowed to escape.
However, in the method described in Japanese Laid Open Patent (Showa) 60-208847 because holes are punched in the moulding compound at the back of the semiconductor element, not only is the lower part of the die-pad, on which the semiconductor element is mounted, exposed to the outside, but when the semiconductor package as a whole is exposed to high temperature, reduction of adhesion between the moulding compound and the die-pad will occur. As a result, it is considered that there is a risk of an adverse effect on the semiconductor element due to corrosion commencing at the peeled section.